Ramsey Electronics FZ-146 Specifications download pdf (Page 106)

FX 146 • 106

R48 and C85 form yet another low pass filter to ensure that any 5 KHz

"whine" will not get into the VCO. Because the DC charge developed in C85

(.1 uf) would slow down the PLL during major frequency swings, such as just

going from transmit to receive, D8 and D10 are set up back-to-back across

voltage dropping R48.

Whenever there is a major frequency shift (which means a significant VCO

control voltage change), one way or the other, one diode or the other is

switched on to short out R48 and discharge C85. This lets the PLL re-lock

instantly; C85 recharges and the diodes become no factor in the circuit. The

"lock detect" output (pin 28) of this Motorola PLL IC is a fine feature that

could be used many different ways in this circuit. We could have set it up to

tell an LED just to alert you that you are "UL" (unlucky, unlocked??) Instead,

we decided to protect your investment in the transmitter RF section of your

transceiver and keep our FCC smiling. The lock detector gives a strong

series of pulses when the PLL is unlocked. When the PLL is locked, only a

tiny sawtooth wave appears at pin 28. The "lock detect" voltage is watched

by U5:B. If "unlock" pulses appear, they are integrated through R90 and C96

as a fairly clean DC voltage charge built up in C96. If this charge causes

U5B to swing low, bias is removed from Transmit Buffer Q10. No damage is

done, and no offending signals can be emitted.

We've toured "The Loop." Now, let's build it and enjoy what it can do!

STAGE G: PLL SYNTHESIZER CIRCUIT ASSEMBLY

Since our most immediate goal is a functioning, programmable receiver, it is

useful to know that the receiver portion could work fine WITHOUT the four

binary adder IC's (U7-U10) or the secondary diode programming matrix. In

practice, this proposition need NOT be pursued, because it would require 16

wire jumpers to connect the A inputs of the adders to the summing outputs.

Also, the programming formula would involve addition of the receiver IF

frequency. For example, to receive 146.52 MHz., we would have to

determine N as (146520 - 21400) ÷ 5. Consequently, we can see that it will

actually EASIER to install the 4 IC's, install diodes in the RECEIVE line of

the second matrix and proceed to find "N" simply by dividing our desired

frequency by 5 KHz.

CONSTRUCTION PROCEDURE NOTE:

The suggested order of assembly for the PLL Frequency Synthesizer portion

of your transceiver is exactly that: a suggestion. This stage involves some

repetitive work that may seem extra easy, but it also can become easier to

make mistakes: skipping connections, causing solder bridges, etc. Some

builders may prefer to push ahead and do all of the repetitive soldering as a

single operation, while others do better work with frequent breaks in the

phases that involve repetition of steps. The suggested order of assembly is

for the benefit of the latter group. If you wish to proceed differently, feel free

to do so. Just be sure to check off the respective assembly steps as you

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Ramsey Electronics FZ-146 Specifications Page 106

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