Ramsey Electronics FZ-146 Specifications download pdf (Page 37)

FX-146 • 37

EXAMPLE 2: RECEIVER OSCILLATOR FREQUENCY

We know from previous circuit discussion that the PLL synthesizer must run

21.4 MHz lower when in receive mode. Two things must be done to do this;

first, we switch out varactor diode D3 to allow the VCO L-C circuitry to tune

21.4 MHz lower, and secondly, program in a 'minus' 21.4 MHz offset to the

synthesizer. This offset is permanently programmed into the matrix because

the 21.4 MHz 1st IF is integral to the FX receiver design. Look closely at the

Receive offset diode row and see why the diodes are installed the way they

are.

N = 21400 ÷ 5 KHz = 4,280

Binary code for N=4,280

Now, invert all the bits:

1 0 1 1 1 1 0 1 0 0 0

Add 1:

1 0 1 1 1 1 0 1 0 0 1

You'll see this is the number programmed into the Receive offset matrix line

for a minus 21.4 MHz offset.

EXAMPLE 3. TWO'S COMPLEMENT WITH CARRY

For illustration purposes, we'll pick an odd-ball offset such as 640 KHz. In

this case, N = 640 ÷ 5 KHz = 128.

Binary code for N=128

8192 4096 2048 1024 512 256 128 64 32 16 8

0 1 0 0 0 0 1 0 1 1 1

8192 4096 2048 1024 512 256 128 64 32 16 8

0 0 0 0 0 0 1 0 0 0 0

Invert all bits: 1 1 1 1 1 1 0 1 1 1 1

Add 1: + 1

Sum at '8' bit position, carry 1 1 0

Sum at '16' bit position, carry 1 1 0 0

Sum at '32' bit position, carry 1 1 0 0 0

Sum at '64' bit position, carry 1 1 0 0 0 0

Sum at '128', no carry needed 1 0 0 0 0

Final result: 1 1 1 1 1 1 1 0 0 0 0

1 2 ... 32 33 34 35 36 37 38 39 40 41 42 ... 144 145

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Ramsey Electronics FZ-146 Specifications Page 37